Method and system for utilizing perovskite material for charge storage and as a dielectric

ABSTRACT

A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material. In a second aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first doped well and located between the two bitlines.

CROSS-REFERENCE TO RELATED APPLICATION

Under 35 USC §120 this application is a continuation application and claims the benefit of U.S. patent application Ser. No. 13/500,301, filed Apr. 4, 2012, entitled “Method and System for Utilizing Perovskite Material for Charge Storage and as a Dielectric,” which is a US National Stage Application of International Application No. PCT/US2011/030382, filed Mar. 29, 2011, entitled “Method and System for Utilizing Perovskite Material for Charge Storage and as a Dielectric,” which claims the benefit of U.S. provisional patent application Ser. No. 61/318,684, filed Mar. 29, 2011, and is related to Application No. 61/234,183, entitled “Heterojunction Oxide Non-Volatile Memory Device,” filed Aug. 14, 2009, and Application Number PCT/US 2010/045667, entitled, “Heterojunction Oxide Non-Volatile Memory Device,” filed on Aug. 16, 2010, all of which are incorporated by reference herein.

FIELD OF THE INVENTION

The present invention relates generally to memory devices, and more particularly to a memory device that includes heterojunction oxide material.

BACKGROUND OF THE INVENTION

As Moore's Law has been predicting, the capacity of memory cells on silicon for the past 15-20 years has effectively doubled each year. Moore's Law is that every year the amount of structures or gates on a silicon wafer will double, but the price will essentially stay the same. And in some cases, the price will even erode. As these memory cells continue to shrink, the technology is starting to reach a barrier know as the quantum limit, that is, they are actually approaching molecular boundaries, so the cells cannot get any smaller.

Disk drives have been the dominant prime storage in terms of peak capacity, because storing individual domains (magnetic transition sites) on the disk drives unlike semiconductor memory cells disk memory sites do not require connections to get in and out of those domains. Now, in recent history, semiconductor resolutions apply feature geometries with 90 nanometer feature resolutions progressing to 45 and 25 nanometer feature size sizes, with these feature capabilities, the memory cell size, and chip capacity equation changes. Furthermore, certain semiconductor memory technologies have applied a principal of geometric redundancy, where a multiple of data bits may be stored in a single cell. This property of a memory cell to support a multiple of values is sometimes referred to as its dynamic range. To date, memory cells have abilities to support a dynamic range anywhere between 1 and 4 bits, which provides multiples of storage per memory cell. These combined properties of semiconductors have increased capacities and costs, and they are now able to directly compete with disk drives.

Another issue associated with semiconductor memory manufacturing has been the substantial costs of the semiconductor foundries which can run up to more than a billion dollars to establish with amortizing expenses, thereby inflating the unit cost of memory chips. In recent history, this represented price barriers compared with cost per capacity of a disk drive file. Now, with advances in foundry resolutions enabling smaller cell sizes and the geometric redundancy of multiple bit-level per memory cell semiconductor memory is actually cheaper per unit cost, and substantially more rugged in terms of high G forces than memory files on a disk drive.

In Flash memories, there have been improvements in the Moore's Law effect but that has become a diminishing proposition because as the cells started getting smaller and smaller, write cycle limitations and ability to support dynamic ranges are diminished.

So basically, as characterized in recent press review, Flash memory is hit the proverbial wall in increasing data capacity per unit cost, as the quantum limit is approached.

But another issue with Flash memory is its limitations in write speeds. In order to compete with disk drive performance, the memory cells word structure is configured to switch in parallel. Another issue is the number of write cycle limitations the cell will tolerate before it permanently fails. Prior to the substantial reduction in cell size, it was approximately in the range of one million, however, as the foundry feature size resolutions reduced in size, rewrite cycle diminished to approximately 100,000 write cycles. For most non-prime storage applications that may be practical. However, for SRAM and DRAM applications where you're actually exchanging data at substantial repetition rates, several times per microsecond.

Accordingly, what is desired is a memory system and method which overcomes the above-identified problems. The system and method should be easily implemented, cost effective and adaptable to existing storage applications. The present invention addresses such a need.

SUMMARY OF THE INVENTION

A memory is disclosed. In a first aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material.

In a second aspect the memory comprises a first doped well; two wells of appropriate doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first dopedwell and located between the two bitlines.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates hysteresis polarization of a memory which includes a ferroelectric material.

FIG. 2 is a diagram of a memory in accordance with the present invention.

FIG. 2A illustrates programming the memory of FIG. 2.

FIG. 2B illustrates erasing data from the memory of FIG. 2.

FIG. 2C illustrates reading data from the memory of FIG. 2.

FIG. 3 is a diagram of wherein the Perovskite material is used as a dielectric material in a capacitor in a memory.

FIG. 4 is a circuit diagram of the memory of FIG. 2.

DETAILED DESCRIPTION

The present invention relates generally to memory devices, and more particularly to a memory device that includes a heterojunction oxide material. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

The present invention is directed to a memory device. The memory device can be utilized in a variety of applications from a free standing nonvolatile memory to an embedded device in a variety of applications. These applications include but are not limited to embedded memory used in a wide range of SOC (system on chip), switches in programmable or configurable ASIC, solid state drive used in computers and servers, memory sticks used in mobile electronics like camera, cell phone, Ipod etc. More particularly, many of the embodiments disclosed herein will include PCMO as one of the metal oxide layers. It is well understood by one of ordinary skill in the art that the present invention should not be limited to this metal oxide layer or any other layer disclosed herein. The key element is that the formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Perovskite material, such as PCMO, has a ferroelectric property. That means the polarization of the material has a hysteresis effect as shown in FIG. 1. The hysteresis effect is due to electric dipoles formed by aligning charge against external field.

This type of material can utilized as part of a NAND/NOR type memory or a DRAM memory. To describe each of these uses in more detail refer now to the following description in conjunction with the accompanying drawings.

NAND/NOR Type Memory

In this embodiment, the Perovskite material is used to replace a charge trap layer such as SixN (or float gate) in a typical NAND/NOR memory. FIG. 2 is a diagram of one embodiment of a memory 100 in accordance with the present invention. The memory includes a Pwell 102 and two Nwells 104 implanted therein. Bitlines 108 a and 108 b are provided on top of the Nwells 104. A PCMO layer 110 is provided over the Pwell 102 between the two Nwells 104 a and 104 b. A PCMO layer 110 that could be utilized in memory 100 is disclosed in PCT Patent Application PCT/US2010/045667, entitled “Heterojunction Oxide Non-Volatile Memory Device,” and assigned to the assignee of this application. A wordline 112 is provided over the PCMO 110.

One of ordinary skill in the art readily recognizes that the device can be in a different configuration and that would be within the spirit and scope of the present invention. Accordingly the memory device could include a Nwell with two Pwells implanted therein and that would be within the spirit and scope of the present invention. The advantage of this type of memory is lower program/erase voltage (−5V or less) (compared with >10V of conventional technology), faster (<100 ns) (compared with 10 us or more for conventional method). In addition, an extra layer can be added between PCMO 110 and conduction channel 114 to prevent charge flow through gate. To describe the operation of the memory 100 refer now to the following description in conjunction with the accompanying Figures.

Program

Programming the device 100 is described in conjunction with FIG. 2A. A magnetic field is applied from the gate that can induce a dipole in PCMO layer 110. The dipole can be induced by adding a positive voltage say 5V at the gate and the ground substrate. Therefore the threshold voltage (Vt) of the memory 100 is reduced.

Erase

Erasing data from the device 100 is described in conjunction with FIG. 2B. During erasure a negative magnetic field from the gate is applied that can reduce the dipole in PCMO layer 110. Therefore the threshold voltage (Vt) of the memory 100 is increased.

Read

Reading data from the memory 100 is described in conjunction with FIG. 2C. The memory is read by sensing current at a drain with smaller gate voltage Vg (for example 2V), and drain voltage Vd (for example 1.2V). The drain current Id indicates the state of the device. Higher current (smaller Vt) may be defined as state “1”, otherwise, it is state “0”. The device is read by sensing current at the drain with smaller gate voltage Vg, and drain voltage Vd.

Ferroelectric Memory

FIG. 3 is a diagram of wherein the Perovskite material is used as a dielectric material in a capacitor in a Ferroelectric memory 200. The memory 200 includes a Pwell 202 and two Nwells 204 implanted therein. Bitlines 208 a and 208 b are provided on top of the Nwells 104. A POMO layer 210 is provided within the bitline 208 b. A POMO layer 210 that could be utilized in memory 200 is disclosed in PCT Patent Application PCT/US2010/045667, entitled “Heterojunction Oxide Non-Volatile Memory Device,” and assigned to the assignee of this application. A wordline 212 is provided over the Pwell 202 between the bitlines 208 a and 208 b. One of ordinary skill in the art readily recognizes that the device can be in a different configuration and that wuld be within the spirit and scope of the present invention.

Accordingly, the memory device could include a Nwell with two Pwells implanted therein and that would be within the spirit and scope of the present invention. The advantage of this type of memory 200 is much longer data retention to reduce refresh than in a conventional DRAM/SRAM, therefore significantly improving energy efficiency.

The memory cell 200 is quite similar to a convnetional DRAM cell. Both cells use the wordline and the bitline with the same topology. The only difference between the two cells is the driveline in the memory 200 that does not exist in the DRAM cell. The function of each line during the write/read operations of the memory 200 is described in the following description in conjunction with the accompanying figure.

FIG. 4 is a circuit diagram of the memory 200. In order to write a binary digit 0 (positive polarization state) to the memory, a positive voltage (normally the full power supply voltage, VDD) is applied to the bitline while the driveline is grounded and the wordline is asserted. In writing a binary digit 1 (negative polarization state), a positive voltage (VDD) is applied to the driveline while the bitline is grounded and the wordline is asserted. Note that a negative voltage would be required on the bitline to produce the same voltage across the POMO capacitor if the driveline were grounded. Also note that the equivalent circuit in the write operation is the POMO capacitor in series with the access transistor ON resistance. Consequently, there is an effective time constant that limits the writing speed.

The memory 200 can be read by floating the bitline and applying a positive voltage (VDD) to the driveline while asserting the wordline. If the initial polarization state of the capacitor is negative (positive), reading the memory develops a relatively large (small) signal on the bitline. Since this operation is destructive, the data must be written back into the cell after each read (data restore). The equivalent circuit in the read operation is the PCMO capacitor in series with the bitline capacitor. Therefore, the capacitance ratio of the bitline to the PCMO capacitor determines the available voltage for polarization switching of the PCMO capacitor. A ratio of 2:1 is normally suggested for 5V power supply operation. Higher ratios will provide larger voltage for the polarization switching but, at the same time, reduces the voltage available for sensing.

Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims. 

1. A memory comprising: a first doped well; two wells of opposite doping implanted in the first doped well; two bitlines located on top of the two wells; a Perovskite material on top of the first doped well and located between two biltines; and a wordline located above the Perovskite material.
 2. The memory of claim 1, wherein the first doped well comprises a Pwell and the two wells comprise two Nwells.
 3. The memory of claim 1, wherein the first doped well comprises an Nwell and the two wells comprise two Pwells.
 4. The memory of claim 1, wherein the Perovskite material comprises a PCMO layer.
 5. A memory comprising: a first doped well; two Nwells implanted in the Pwell; two bitlines located on top of the two Nwells; a Perovskite material located within one of the two Nwells; and a wordline located between the two bitlines.
 6. The memory of claim 5, wherein the first doped well comprises a Pwell and the two wells comprises two Nwells.
 7. The memory of claim 5, wherein the first doped well comprises an Nwell and the two wells comprise two Pwells.
 8. The memory of claim 5, wherein the Perovskite material comprises a PCMO layer.
 9. A system comprising one or more of the memory of claim
 1. 10. A system comprising one or more of the memory of claim
 5. 11. A memory comprising: a first doped well; two wells of opposite doping implanted in the first doped well; two bitlines located on top of the two wells; a Perovskite material connected to one of the bitlines; and a wordline located above the two wells of opposite doping.
 12. The memory of claim 11, wherein the first doped well comprises a Pwell and the two wells comprise two Nwells.
 13. The memory of claim 11, wherein the first doped well comprises an Nwell and the two wells comprise two Pwells.
 14. The memory of claim 11, wherein the Perovskite material comprises a PCMO layer.
 15. A system comprising one or more of the memory of claim
 11. 16. A method for providing a memory, comprising providing a transistor; providing a capacitor comprising Perovskite material, wherein the capacitor is connected to a side of the transistor; providing a wordline, connected to a gate of the transistor; providing a bitline, connected to a side of the transistor not connected to the capacitor; and providing a driveline, connected to the capacitor.
 17. The method of claim 16, comprising writing the memory by: applying a positive voltage to the bitline; connecting the driveline to ground; and asserting the wordline.
 18. The method of claim 16, comprising writing the memory by: applying a positive voltage to the driveline; connecting the bitline to ground; and asserting the wordline.
 19. The method of claim 16, comprising reading the memory by: floating the bitline; applying a positive voltage to the driveline; and asserting the wordline. 